Hello guys!
Let's do our first design using the demo board.
I'll explain step-by-step how to create a new project, develop our code and synthesize it using ISE 13.3 installed in the last post.
1) First we have to create a project.Go to File > New Project...
Name: helloworld
Top-level source type: HDL
2) Then we have to select device
Family: Spartan3E
Device: XC3S1600E
Package: FG320
Speed: -4
Simulator: Isim(VHDL/Verilog)
Preferred Language: VHDL
VHDL Source Analysis Standard: VHDL-200X
3) Now at panel left "Design", right click over : xc3s1600e-4fg320 and select "New source..."
4) Select "VHDL module" and type filename: helloworld.
5) We don't need to enter right now the port name. We can define after in the code. Click NEXT and then FINISH.
Now we can start make some code:
This program is very simple. The leds will count in binary mode, upwards when updown is '1' and downwards when '0'.
At lines 1, 2 and 6, as like in C the #include statement. The STD_LOGIC_1164 define most of standard logic levels like high, low, Z, X, etc. The NUMERIC_STD is used to be able to use functions with signed and unsigned types.
We define our entity at line 13 and it has only 3 pins: clk, led and updown where clk and updown are input type and led an 8 bits output type.
As our circuit is a synchronized one, we will perform some action only in a rising edge of clock. It's done at line 28 with the reserved word rising_edge.
And finally, as our clock use a 50MHz crystal, we have to have a pre-scale counter to be able to see the leds changing, otherwise, we would see the 8 leds always on. We use for this purpose the signal cnt that counts from 0 until CNT_MAX.
Now, to synthesize our circuit, select View: Implementation and menu Process > Implement Top Module.
It will take a while because synthesize a circuit is very different of compiling a code. If you want to know more about, there are lots of sites out there that explains the difference. Just google it!
Next post I'll show you how to simulate our design, how to assign to the physical pins the signals that we defined in our code, how to generate the bitstream that will be programmed in the FPGA and finally how to program the FPGA demo board!
Marcelo
Read more ►
Let's do our first design using the demo board.
I'll explain step-by-step how to create a new project, develop our code and synthesize it using ISE 13.3 installed in the last post.
1) First we have to create a project.Go to File > New Project...
Name: helloworld
Top-level source type: HDL
2) Then we have to select device
Family: Spartan3E
Device: XC3S1600E
Package: FG320
Speed: -4
Simulator: Isim(VHDL/Verilog)
Preferred Language: VHDL
VHDL Source Analysis Standard: VHDL-200X
3) Now at panel left "Design", right click over : xc3s1600e-4fg320 and select "New source..."
4) Select "VHDL module" and type filename: helloworld.
5) We don't need to enter right now the port name. We can define after in the code. Click NEXT and then FINISH.
Now we can start make some code:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity helloworld is port (clk : in STD_LOGIC := '0'; led : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); updown : in STD_LOGIC := '1' ); end helloworld; architecture Behavioral of helloworld is constant CLK_FREQ : integer := 50000000; constant BLINK_FREQ : integer := 1; constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1; signal value : std_logic_vector (7 downto 0) := "00000000"; signal cnt : unsigned (24 downto 0) := (others => '0'); begin process(clk) begin if rising_edge(clk) then if cnt = CNT_MAX then cnt <= (others =>'0'); case updown is when '1' => value <= std_logic_vector(unsigned(value) + 1); when others => value <= std_logic_vector(unsigned(value) - 1); end case; else cnt <= cnt + 1; end if; end if; end process; led <= value; end Behavioral;
This program is very simple. The leds will count in binary mode, upwards when updown is '1' and downwards when '0'.
At lines 1, 2 and 6, as like in C the #include statement. The STD_LOGIC_1164 define most of standard logic levels like high, low, Z, X, etc. The NUMERIC_STD is used to be able to use functions with signed and unsigned types.
We define our entity at line 13 and it has only 3 pins: clk, led and updown where clk and updown are input type and led an 8 bits output type.
As our circuit is a synchronized one, we will perform some action only in a rising edge of clock. It's done at line 28 with the reserved word rising_edge.
And finally, as our clock use a 50MHz crystal, we have to have a pre-scale counter to be able to see the leds changing, otherwise, we would see the 8 leds always on. We use for this purpose the signal cnt that counts from 0 until CNT_MAX.
Now, to synthesize our circuit, select View: Implementation and menu Process > Implement Top Module.
It will take a while because synthesize a circuit is very different of compiling a code. If you want to know more about, there are lots of sites out there that explains the difference. Just google it!
Next post I'll show you how to simulate our design, how to assign to the physical pins the signals that we defined in our code, how to generate the bitstream that will be programmed in the FPGA and finally how to program the FPGA demo board!
Marcelo
